High-speed digital data links may suffer from inter-symbol interference, especially in situations in which loss, reflections or other imperfections exist in the transmission channel. Inter-symbol interference may have the effect that the signal received during a given clock cycle includes a linear combination of (i) the bit transmitted during the corresponding clock cycle at the transmitter, and (ii) the bits transmitted during a number of preceding clock cycles. The effects of inter-symbol interference may be mitigated using a technique referred to as decision feedback equalization (DFE) which involves correcting the received signal at the sampling point, during each clock cycle, with a linear combination of the bits received during a number of preceding clock cycles.
A serial receiver may include two slicers, e.g., a data slicer and a crossing slicer. The serial signal received by the data slicer may be corrected by a sum of taps calculated from the previously received bits and a model of the channel characteristics. The correction from the most recently received bit (or “last bit”), which is referred to as the first data tap, may be generated using a technique referred to as predictive decision feedback equalization (predictive DFE, which may also be referred to as speculative DFE or loop-unrolled DFE), in which two correction terms are calculated, one corresponding to a received 1 in the last bit, and one corresponding to a received 0 in the last bit; the appropriate one of these two correction terms is then selected using a multiplexer (MUX) once a binary value for the last bit is available. A similar correction of the serial signal received by the crossing slicer may be performed, but the taps for the data slicer may not provide an accurate estimate of the required correction for the crossing slicer, which samples at different points in time than the data slicer. Thus, there is a need for a system providing improved mitigation of inter-symbol interference in a crossing slicer.